Tranche 4c of Ship 8 sink-side RGBA. Wiring-only PR — adds Yuv440p (4:4:0 planar, 8-bit) RGBA output by reusing the yuv_444_to_rgba_row dispatcher that shipped in PR #19. No new kernel code anywhere in the crate; per-row math is identical to 4:4:4 (full-width chroma) — only the walker reads chroma row r / 2.

Smallest tranche of Ship 8 so far: 2 files modified, +222 / -9 net.

Scope

Usage:

```rust
use colconv::{
frame::Yuv440pFrame,
sinker::MixedSinker,
yuv::{Yuv440p, yuv440p_to},
ColorMatrix,
};

let frame = Yuv440pFrame::new(&y_plane, &u_plane, &v_plane, w, h, w, w, w);
let mut rgb = vec![0u8; (w * h * 3) as usize];
let mut rgba = vec![0u8; (w * h * 4) as usize];
let mut sinker = MixedSinker::::new(w as usize, h as usize)
.with_rgb(&mut rgb)?
.with_rgba(&mut rgba)?;

// Both buffers requested → YUV→RGB math runs once via yuv_444_to_rgb_row,
// RGBA derived via expand_rgb_to_rgba_row (Strategy A from PR #20).
yuv440p_to(&frame, /full_range=/ true, ColorMatrix::Bt709, &mut sinker)?;
```

What's in this PR

Public API

• `MixedSinker::with_rgba(&mut [u8])` / `set_rgba` — format-specific impl block in `src/sinker/mixed/planar_8bit.rs` (per the PR feat(sinker): Ship 8 — Yuv420p RGBA output via const-ALPHA template #16 safety pattern: attaching RGBA to a sink that doesn't write it is a compile error, not a silent stale-buffer bug).

Kernel work

Zero. 4:4:0 reuses the existing 4:4:4 dispatchers because the per-row math is identical (full-width chroma; the half-height layout is a walker concern — yuv440p_to reads chroma row r / 2 and feeds Yuv440pRow to process, which receives full-width U/V slices indistinguishable from 4:4:4 to the kernel).

MixedSinker integration

`MixedSinker::process` rewritten for Strategy A output mode resolution (mirrors the pattern landed in PR #20 across all 8 prior wired families):

• RGBA-only (no RGB / HSV): dedicated `yuv_444_to_rgba_row` directly into the output buffer.
• RGB / HSV (± RGBA): `yuv_444_to_rgb_row` once into `rgb_row` (or `rgb_scratch`), then HSV derivation if requested, then `expand_rgb_to_rgba_row` if RGBA also requested.

The `compile_fail` doctest negative example moved forward from `MixedSinker::::with_rgba` to `MixedSinker::::with_rgba` (next not-yet-wired format — Tranche 5 high-bit-depth 4:2:0).

Doc updates

`docs/color-conversion-functions.md` § Ship 8 tranche tracker — mark 4c as the active PR, 4b as ✅ shipped (PR #20), promote tranche 5 to "next".

Tests

+4 lib tests on aarch64 (479 vs. 475 in PR #21):

No per-backend equivalence tests added — the SIMD paths exercised here are the existing `yuv_444_to_rgba_row` family, already covered by PR #19's per-backend Yuv444p RGBA tests across all 5 SIMD backends.

Local results (aarch64 macOS): 479 lib tests + 1 doctest pass; wasm32 + x86_64 cross-targets compile clean; clippy reports zero warnings.

What's deferred

• Tranche 5 — high-bit-depth 4:2:0 (`Yuv420p9/10/12/14/16`, `P010/P012/P016`). Per the post-prod MAM frequency table in `docs/color-conversion-functions.md` § 2a, this is ranked feat(NV12): NV12(semi-planar 4:2:0) + fallible PixelSink contract #2 priority unlock (after tranche 6, the 10-bit 4:2:2 ProRes / DNxHR family).
• `with_rgba_u16` ships in tranches 5–7 (where `u16` output exists).
• YUVA source frames (Ship 8b) — independent follow-up; copies alpha through from the source plane instead of defaulting to `0xFF`.
• Strategy B (combined kernel writing both RGB and RGBA stores per pixel) — future optimization, only worth shipping if profiling shows the L1-readback step in the current Strategy A fan-out matters.
• Cleanup PR follow-ups still tracked in the cleanup memory: `_impl` visibility tightening (Copilot feat(NV12): NV12(semi-planar 4:2:0) + fallible PixelSink contract #2 from PR feat(sinker): Ship 8 — Nv24/Nv42 RGBA + Strategy A RGB→RGBA fan-out #20 review) and RGBA-plane bounds-check helper extraction across all 9 `process` impls (Copilot feat(yuv420p10): 10-bit YUV 4:2:0 planar → u8 + native u16 RGB #4). Should land before tranches 5+ start adding more high-bit-depth families.

Test plan

• CI green on `test`, `test-sde-avx512`, `cross`, `coverage`, `clippy`, `build`, `miri-*` jobs.
• Per-tier coverage matrix exercises SSE4.1 / AVX2 / scalar paths via existing `colconv_disable_*` rustflags (no new SIMD code, but the dispatcher routes through the same Yuv444p backends).
• Verify Yuv440p → both-buffers (RGB + RGBA) pipeline end-to-end with a real frame (gray + non-gray patches).
• `cargo doc --lib --no-deps` clean (no new doc warnings vs. main).

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